HIRING NOW
🚨 Hiring: ASIC RTL Design Engineer
📍 Bangalore | Hyderabad | Kochi
Experience
5–22 Years
Notice Period
Immediate to 60 Days
We’re looking for experienced ASIC RTL Design Engineers with strong hands-on experience in RTL Design, IP Design, SoC Integration, and Microarchitecture.
What We’re Looking For
- Strong RTL coding experience using Verilog/SystemVerilog
- Experience in IP, Subsystem/Cluster and SoC-level integration
- Good understanding of ARM Cortex-M7 (CM7)
- Strong knowledge of RTL quality checks – Lint & CDC
- Good understanding of AMBA protocols – AXI, AHB, ATB, APB
- Knowledge of timing concepts
- Experience with one or more protocols: PCIe, DDR, Ethernet, I2C, UART, SPI
Tools
Good to Have
- Synthesis and Low Power knowledge
- Processor architecture / ARM debug architecture
- Experience supporting Verification, Physical Design, DFT and Software teams
- Ability to debug issues across multiple subsystems