STA LEAD / TIMING LEAD

STA Lead / Timing Lead – Job Opening
🚀 CURRENT OPENING

STA Lead / Timing Lead

Join our semiconductor engineering team and work on advanced technology designs, timing closure, STA analysis and signoff.

📍 Location Bengaluru, Karnataka
💼 Experience 10–15 Years
🕐 Notice Period 0–30 Days
📌 Employment Permanent
💰 Budget Open

📋 Job Summary

We are looking for an experienced STA Lead / Timing Lead with strong expertise in Static Timing Analysis (STA), timing closure, and signoff for advanced semiconductor designs. The ideal candidate will have strong hands-on experience with STA tools, MMMC analysis, timing constraints, high-frequency timing closure, ECO implementation, and full-chip timing signoff.

🔑 Key Responsibilities

  • Lead Static Timing Analysis (STA) and timing closure activities at block and full-chip levels.
  • Define and validate timing modes, corners, and signoff requirements for full-chip STA.
  • Perform MMMC analysis across multiple modes and corners.
  • Drive high-frequency timing closure in the GHz range.
  • Analyze and resolve setup, hold, recovery, and removal violations.
  • Develop, review, and validate SDC constraints.
  • Support DFT mode timing requirements for timing signoff.
  • Generate and implement timing ECOs in collaboration with Physical Design/PnR teams.
  • Automate STA flows and analysis using TCL scripting.
  • Perform OCV/AOCV/POCV analysis for accurate timing signoff.
  • Collaborate closely with PnR, Constraints, DFT, and Physical Design teams.
  • Support full-chip STA closure and signoff.
  • Perform Signal Integrity (SI), crosstalk delay, and noise analysis where required.

🛠️ Key Skills Required

Deep expertise in PrimeTime, PT-DMSA/PTECO, Tempus, and Tweaker
Strong knowledge of timing corners, modes, and MMMC
Expertise in OCV / AOCV / POCV analysis
Experience with GHz-range high-frequency timing closure
Block-level and full-chip STA closure experience
Strong understanding of DFT timing modes and signoff requirements
Good understanding of Physical Design / PnR flow
Strong SDC authoring and validation skills
Mandatory: TCL scripting for STA flow automation
Hands-on experience with manual and automated ECO generation and delivery
SI / crosstalk delay and noise analysis experience preferred

👤 Ideal Candidate Profile

  • 10–15 years of overall VLSI/Semiconductor experience.
  • Ideally 8–12 years of dedicated STA / timing closure experience.
  • Experience with advanced technology nodes, preferably 2nm / 3nm / 4nm.
  • Strong hands-on experience in timing signoff and closure methodologies.
  • Experience working with PnR, Constraints, DFT, and Physical Design teams.
  • Strong analytical and debugging skills.
  • Candidates who can join within 0–30 days are preferred.

✅ Candidate Screening Checklist

📩 Apply Now

Interested candidates can share their updated CV/profile with our recruitment team.

Please share your updated resume along with total experience, relevant STA experience, current location, and notice period.

Apply for this position

Allowed Type(s): .pdf, .doc, .docx
Scroll to Top