Role Summary

We are looking for a senior DFT professional to lead DFT strategy, execution, and team delivery for complex SoCs and IPs.

This role requires strong hands-on DFT expertise combined with technical leadership, team management, technical ownership, and cross-functional coordination.

Key Responsibilities

• Lead end-to-end DFT architecture, implementation, verification, and signoff for SoC/IP programs.
• Define and own DFT strategies covering Scan, JTAG, iJTAG, BSCAN, ATPG, and MBIST.
• Review and approve DFT plans, test architectures, coverage targets, and implementation strategies.
• Drive ATPG, MBIST, DFT simulation, debug, and signoff activities.
• Lead silicon bring-up, DFT debug, failure analysis, and yield improvement initiatives.
• Manage and mentor a team of DFT engineers, including task allocation, reviews, and technical guidance.
• Conduct technical reviews with Design, Physical Design, Validation, and Product teams.
• Drive schedules, risk management, and DFT delivery commitments across projects.
• Establish and improve DFT methodologies, best practices, and automation.
• Interface with customers and management on DFT status, issues, risks, and technical plans.

Required Technical Skills

Leadership & Management

• Proven experience as a DFT Team Lead, Technical Lead, or DFT Manager.
• Experience leading, mentoring, and developing DFT engineers.
• Strong ownership of technical reviews and DFT signoff.
• Experience planning and tracking deliverables across multiple projects.
• Strong stakeholder management and cross-functional coordination skills.
• Ability to drive technical decisions and resolve complex DFT issues.

Good to Have

• Experience with Low-Power DFT, IJTAG networks, and advanced test compression.
• Experience working on multiple SoCs or large, complex semiconductor designs.
• Customer-facing or program leadership experience.

Education